2. Design an excess-3 to BCD code converter using minimum number of NAND gates.

3(a) How can we implement preset and clear inputs in a flip-flop? Explain with the help of a diagram and list their uses.

3.(b) Design a Mod 9 counter using T flip-flops.

4. (a) Explain internal organization of 16×2 memory chips using suitable diagrams. Calculate the maximum rate at which data can be stored and read for a memory having following timing parameters

(b) Differentiate between Word Capacity and Word Size. Design a 16×8 CAM, using 8×2 CAM chips.

5(a) Define resolution, linearity, accuracy and settling time of D/A converters. A typical D/A converter has a full-scale analog output of 10 V and accepts 6 binary bits as input. What will be the voltage corresponding to each analog step?

(b) Design a 3-bit parallel comparator A/D converter that provides output in 2’s complement format.

6.(a) Design a BCD to 7-segment display decoder circuit using logic gates. (b) Design full adder using the following: (i)8:1 mux (ii) 4:1 mux

7(a) On the following graph, inputs CLK and D are shown: They are inputs to a D latch and a positive edge triggered D flip-flop. Assuming initial output 0, draw the output waveform for flip-flop and latch. Do the two outputs differ? If so, why?

(b) Explain SIPO and SISO operations of shift register with relevant logic diagrams and truth tables.

8. (b) Implement the following CMOS logics : (i) AB(A+B) (ii) (CD) + B)A

(9) (a) What are weighted, non-weighted, cyclic and self-complementary codes? Explain each with examples.

(b) Find the values of X in the following conversions: 2×3 (i) (95.10)10 to (X)2 (ii) (45.70)8 to (X)2 (in) (168.16)g to (X)16