BEU Computer Organization & Architecture question paper solution

BIHAR Engineering university computer science engineering previous year question. BEU previous year question. computer organization 2022 cse question paper solution. BEU pyq solution

2. (a) List and briefly define the main structural components of a computer.

(b) Discuss the design and logic of a microprogram sequence.

3. Consider processor hypothetical 32-bit 22-bit micro- having 32-bit instructions composed of two fields-the first byte contains the opcode and the remainder the immediate operand or an operand address.
(a) What in the maximum directly addressable bytes)? memory capacity (in
(b) Discuss the impact on the system speed if the microprocessor bus has-
(i) a 32-bit local address bus and a 16-bit local data bus, or
ii) a 16-bit local address bus and a 16-bit local data bus.
(c) How many bits are needed for the program counter and the instruction register?

4. (a) A set-associative cache has a block size of four 16-bit words and a set size of 2. The cache can accommodate a total of 4096 words. The main memory size that is cacheable is 64K 32 bits. Design the cache structure and show how the processor’s addresses are interpreted. (b) Explain two techniques for enhancing the performance of computers with multiple execution pipelines.

(B)Explain two techniques for enhancing the performance of computers with multiple execution pipelines.

5. (a) Calculate (72530-13250) using ten’s complement arithmetic. Assume rules similar to those for two’s complement arithmetic.

(B) List and briefly explain five important instruction set design issues.

6. The x86 architecture includes an instruc- tion called decimal adjust after addition (DAA). DAA performs the following sequence of instructions:
if((AL AND OFH)>9) OR (AF = 1) then AL + 6
A F leftarrow0 ;
endif; if (AL > 9FH) OR (CF = 1) then AL leftarrow AL + 60H ;
C F leftarrow1 ;
elsed prac
C F leftarrow O bebige dredi uot lo
endif. 2010
“H” indicates hexadecimal. AL is an 8-bit register that holds the result of addition of two unsigned 8-bit integers. AF is a flag set if there is a carry from bit 3 to bit 4 in the result of an addition. CF is a flag set if there Es a carry from bit 7 to bit 8. Explain the Function performed by the DAA instruction

7. A non-pipelined processor has a clock rate of 2.5 GHz and an average CPI of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHz.
(I)What is the speedup achieved for a typical program?
(II)What is the MIPS rate for each processor?

8. (a) Briefly explain the two basic approaches used to minimize register- memory operations on RISC machines.

(B) A computer has 16 registers, an ALU with 32 operations and a show with 8 operations, all connected to a common bus system.
i) Formulate a control word for a micro-operation.
ii) Show the bits of the control word that specify the micro-operation R4 <— R5 + R6.

9.Let a be the percentage of a program code that can be executed simultaneously by n processors in a computer system. Assume that the remaining code must be executed sequentially by a single processor. Each processor has an execution rate of xMIPS.
(a) Derive an expression for the effective MIPS rate when using the system for exclusive execution of this program, in terms of n, a and x.
(b) If n= 16 and x=4 MIPS, determine the value of that will yield a system performance of 40 MIPS.




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