BEU previous year question solution. BEU organizer , BEU notes, BEU vlsi pyq solution 2022 electrical engineering . Bihar engineering university question paper all branch all semseter
(a) What is depletion mode device?
(b) What is body effect?
(C) What is the cause of storage time in a bipolar transistor?
(d) What is meant by the fan-out of a logic gate?
(e) Charge moves from VDs is applied Towhen.
(F) What is sheet resistance?
(g) What is a dynamic logic?
(h) List different timings used in memory cell.
(i) What do you understand by propagation delay?
(J) What is meant by logical effort?
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2. (a) Explain why the drain current keeps onincreasing even after the V Dear voltagewhereas it should have been fixed for anideal MOS transistor.
(b)What is the physical origin of latch-upproblem in CMOS? How can the latch-up problem be prevented?
3. (a) Explain the method of threshold voltageextraction from the current-voltagecharacteristics of MOSFET.
(b) Consider a MOS system with the following parameters: Gate oxide thickness (t ox )=200 A Gate to substrate contact potential ( phi GC )=0.85 V Substrate doping (N_{A}) = 2 * 10 ^ 15 * c * m ^ – 3Trapped oxide charge (Q_{m}) = q ^ 2 * 10 ^ 11 * C / c * m ^ . Determine the threshold voltage V T 0under zero bias at room temperature(T = 300K) Given: epsilon ax =3.97 epsilon 0 and epsilon Sj =11.7 epsilon 0
4.(a) What do you understand by constant voltage scaling? What is the effect of constant field scaling on (i) power dissipation and (u) delay time?
(b) Explain the method of channel length modulation parameter extraction from the current-voltage characteristics of MOSFET.
5. (a) Define VIL, VIH, VOH and VOL voltage levels in the voltage transfer characteristics of an inverter. Show that the V for a CMOS inverter is given by 2Vout +VTO. PVDD + KRVTO, nVIL =where KR = kn /kp.
(b) Consider a CMOS inverter with the following device parameters: nMOS VTo.n=0.6V Hn Cox = 60μA/v2 PMOS: VTO. P = -0.8 V Hp Cax=20µA/V2Determine the (W/L) ratios of the nMOS and pMOS transistor such that the switching threshold (V) is 1-5 V Given VDD = 3 V, λ = 0.
6.(a) Suppose a unit inverter with three units of input capacitance has unit drive. What is the drive of a 4x inverter? What is the drive of a 2-input NAND gate with 3 units of input capacitance?(b) What is a transmission gate (TG)? Design a circuit for 2-input TG based XOR gate.
7. (a) Explain the problem of charge sharing in dynamic CMOS designs and its probable solution.(b) Compare the BiCMOS logic with CMOS in terms of delay and power consumption. Why was BiCMOS logic used in Intel Pentium and Pentium Pro but discarded in Pentium II?
8. (a) Explain the dual rail domino logic. Design XOR/XNOR gate using dual rail domino logic.(b) Implement the full transmission gates. adder using
9. (a) Explain the working of 4T SRAM cell with neat diagram.
(b) Explain the working of a 3T DRAM with neat diagram.
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